1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including an electro static discharge (ESD) protection element.
2. Description of the Prior Art
As the integration degree of a semiconductor integrated circuit device increases along with the miniaturization and increase in density of elements, the semiconductor integrated circuit device becomes more susceptible to damages due to electro static discharge (hereinafter referred to as “surge”). For example, the surge intruding via a pad for external connection destructs elements, such as an input circuit, an output circuit, an input/output circuit, and an internal circuit, which increases the possibility of reduced performance of elements. To cope with the problem, the semiconductor integrated circuit device includes an electro static discharge (ESD) protection element for protection against the surge. The ESD protection element is provided between the pad for external connection and the input circuit, the output circuit, the input/output circuit, or the internal circuit.
FIG. 8A and FIG. 8B show a configuration of a conventional ESD protection element, wherein FIG. 8A is a plan view, and FIG. 8B is a cross section taken along the line VIIIb-VIIIb of FIG. 8A (see, for example, Japanese Laid-Open Patent Publication No. 2-58262).
In a well region 110 formed in a semiconductor substrate, a diffusion layer 111 and a diffusion layer 112 are formed. The diffusion layer 111 has a conductivity type opposite to that of the well region 110. The diffusion layer 112 has the same conductivity type as that of the well region 110. The diffusion layer 111 and the diffusion layer 112 are arranged facing each other with a dielectric isolation region 113 interposed therebetween. On the diffusion layers 111 and 112, a plurality of contact regions 114 and 115 are respectively formed. The diffusion layers 111 and 112 are respectively connected to electrodes 122 via plugs 121 formed in an interlayer dielectric film 120. The electrode 122 connected to the diffusion layer 111 is connected to a pad 123 for external connection. The electrode 122 connected to the diffusion layer 112 is connected to a power source or a ground.
Upon intrusion of a surge via the pad 123 for external connection, a diode formed by the well region 110 and the diffusion layer 111 is brought into conduction. As a result, the externally intruding surge is led to the power source or the ground connected to the diffusion layer 112, making it possible to protect a circuit which is to be protected.